The present invention relates to a semiconductor apparatus and a method of manufacturing the same and, more particularly, to a semiconductor device with an aligning mark used for photolithography and a method of manufacturing the same.
In a semiconductor device manufacturing process, the steps of forming a deposition film on a semiconductor substrate by oxidation or sputtering, and patterning the deposition film to form an insulating pattern, interconnection pattern, or the like are repeatedly performed. This pattern formation employs a reduction projection exposure apparatus (to be referred to as a stepper hereinafter). This stepper is an apparatus which exposes a resist film formed on the semiconductor substrate by using a reticle having a pattern formed by enlarging a pattern to be actually formed by a predetermined magnification. The resist film exposed by using the stepper is developed to form a resist pattern. By using the resist pattern as an etching mask, the deposition film is processed, thereby forming a micropattern.
To align the relative positions of circuit patterns stacked on each other, when exposing the resist film, the semiconductor substrate and the reticle must be aligned relative to each other. For this purpose, an aligning mark is formed on the semiconductor substrate. The aligning mark is irradiated with light, and its position is detected from light diffracted by it upon irradiation. Then, alignment is performed.
As an example of an aligning mark manufacturing method, a method of manufacturing an aligning mark for a conventional DRAM (Dynamic Random Access Memory) will be described with reference to FIGS. 6 to 8.
As shown in FIG. 6, a field oxide film 102 is formed in an isolation region on a p-type silicon semiconductor substrate, and a gate oxide film (not shown) is formed. Successively, a word line (first lower interconnection layer; not shown) comprised of the first polysilicon layer is formed, and by using the word line, N-diffusion layers (not shown) for forming the source/drain regions of a switching MOS transistor are formed in an element region surrounded by the field oxide film 102 by self-alignment.
The first interlevel insulating film (not shown) is formed on the entire surface of a semiconductor substrate 101, and contact holes (not shown) are formed in the first interlevel insulating film and gate oxide film to reach the N-diffusion layers.
Polysilicon is deposited on the first interlevel insulating film and in the contact holes, and the resultant polysilicon layer is patterned to form bit lines (second lower interconnection layer; not shown) comprised of the second polysilicon layer and plug electrodes (not shown) for connecting the bit lines and N-diffusion layers. The second interlevel insulating film (not shown) is formed on the entire surface of the semiconductor substrate 101.
At this stage, as shown in FIG. 6, a multilayered interlevel film 103 comprised of the word line, the first interlevel insulating film, bit lines, and the second interlevel insulating film is formed in the memory cell region (circuit formation region). The interlevel film 103 has a thickness of, e.g., about 1,000 nm.
When patterning a silicon layer or metal layer, since a circuit pattern is not formed on an aligning mark formation region (e.g., a scribing region), a conductor layer deposited on the aligning mark formation region is removed. Therefore, at the aligning mark region, the first interlevel film 103 is comprised of only the first and second interlevel insulating films. Hence, as shown in FIG. 6, the thickness of the interlevel film 103 in the aligning mark region is smaller than that in the memory cell region.
Contact holes 104 for connecting storage electrodes 105 (to be described later) and the N-diffusion layers (not shown) are formed. Subsequently, as shown in FIG. 7, the storage electrodes 105 made of third polysilicon and with a thickness of about 500 nm to 800 nm are formed in the memory cell region. A capacitor insulating film (not shown) is formed on the interlevel film 103 and storage electrode 105, and after that a plate electrode 106 made of fourth polysilicon is formed on the capacitor insulating film.
A third interlevel insulating film (SiO2 film, BPSG film, or the like) 107 with a thickness of about 500 nm is formed on the entire surface of the semiconductor substrate 101, and etch-back and a reflow process (e.g., in an N2 atmosphere at 850xc2x0 C. for 10 min) are performed to planarize the memory cell region.
After that, W (tungsten) or Al (aluminum) is deposited on the entire surface of the semiconductor substrate 101, and the deposited film is patterned to form interconnection layers 108 in the memory cell region and aligning marks 108a in the aligning mark formation region, as shown in FIG. 8.
A fourth interlevel insulating film 109 (Plasma SiO2 film or the like) with a thickness of about 400 nm is formed on the entire surface of the semiconductor substrate 101, and silica films 110 are formed on the interlevel insulating film 109, thereby planarizing the memory cell region.
At this time, as shown in FIG. 8, since a step of about 900 nm to 1,200 nm is formed between the memory cell region and aligning mark formation region, the thickness of the silica film 110 formed in the aligning mark formation region is larger than those of the silica films 110 formed in the memory cell region. Hence, planarization with reference to the memory cell region cannot sufficiently remove the silica film 110 in the aligning mark formation region, and a large amount of silica (silica films 110) is left there.
Finally, as shown in FIG. 8, a fifth interlevel insulating film 111 (Plasma SiO2 film or the like) with a thickness of about 400 nm is formed on the entire surface of the semiconductor substrate 101. When some layer is formed on the fifth interlevel insulating film 111 and is to be patterned, the aligning marks 108a formed in this manner are irradiated with light, and light diffracted by the aligning marks 108a is detected, so that alignment is performed.
As shown in FIG. 8, if a large amount of silica (silica film 110) is left on the aligning marks 108a, the light diffracted by the aligning marks 108a cannot be detected correctly, and the aligning precision decreases. If the aligning precision decreases, the resist pattern cannot be formed at a desired position, and consequently a micropattern such as interconnections cannot be formed accurately.
When the semiconductor substrate 101 is etched back to remove the silica film 110 on the aligning marks 108a, the memory cell region is further etched, and planarization of the memory cell region is impaired.
As a method of making smaller the step formed between the upper interconnection layer and aligning marks, Japanese Patent Laid-Open No. 11-121327 discloses a method of intentionally leaving an insulating film and conductive layer, which are formed in a circuit formation region, in an aligning mark formation region. This method does not disclose or suggest planarization between upper interconnection layers with silica, or disclose detection of aligning marks by using diffracted light.
It is an object of the present invention to provide a method of manufacturing a semiconductor device having a high aligning precision.
It is another object of the present invention to provide a method of manufacturing a semiconductor device which can be aligned easily.
In order to achieve the above objects, according to the present invention, there is provided a method of manufacturing a semiconductor device having a circuit formation region where a semiconductor circuit is to be formed and an aligning mark formation region where an aligning mark used for alignment of a mask is to be formed, the method comprising the steps of forming a first conductive layer on a semiconductor substrate and thereafter patterning the first conductive layer, thereby forming a circuit pattern in the circuit formation region and leaving the first conductive layer in the aligning mark formation region, forming a first insulating film on the semiconductor substrate including the circuit pattern and the first conductive layer, forming a second conductive layer on the first insulating film and thereafter patterning the second conductive layer, thereby forming an interconnection pattern in the circuit formation region and an aligning mark in the aligning mark formation region, and forming a second insulating film on the interconnection pattern and the aligning mark and thereafter etching back the second insulating film, thereby planarizing the circuit formation region and the aligning mark formation region and removing the second insulating film on the aligning mark.